Cadence expands partnership with TSMC on certified tool flows, silicon-proven UALink IP for advanced nodes

Bitget2026/09/23 19:00

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Cadence expanded its partnership with TSMC to deliver certified design tools and silicon-proven IP for advanced AI and HPC chips.
Tool flows gained certification for TSMC’s A14, A16, N2P nodes, targeting faster tape-outs and improved power, performance, area.
Partnership also supports TSMC 3DFabric wafer-scale, multi-chiplet design flows, including certified die-to-die auto-routing for CoWoS architectures.
Cadence highlighted UALink IP demonstrated on N3P; UCIe-64G taped out on A14; additional IP development extends into Q4 2026.

Disclaimer: This news brief was created by Public Technologies (PUBT) using generative artificial intelligence. While PUBT strives to provide accurate and timely information, this AI-generated content is for informational purposes only and should not be interpreted as financial, investment, or legal advice. Cadence Design Systems Inc. published the original content used to generate this news brief via Business Wire (Ref. ID: 20260923699511) on September 23, 2026, and is solely responsible for the information contained therein.

Disclaimer: The content of this article solely reflects the author's opinion and does not represent the platform in any capacity. This article is not intended to serve as a reference for making investment decisions.

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Cadence expands partnership with TSMC on certified tool flows, silicon-proven UALink IP for advanced nodes

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